On-ASIC Integration: Solving Chip-Level Challenges

The traditional data center architecture of front-panel pluggable optics and copper is reaching its limits. Its long, lossy signal path through multiple interconnection points causes rapidly increasing signal degradation as baud rates rise. The result is a significant shrinkage in practical reach and margin with each generational increase. To meet the demands of 224Gbps-PAM-4 data rates, the industry is responding with on-ASIC integration, an architectural answer that moves I/O directly onto the processor's substrate.  Although it is not required for all 224G systems, this technically complex shift is being addressed now so the architecture can be integrated more broadly when 448G data rates make it unavoidable. This continues a long-running trend that has progressed from traditional board-level routing to cabled near-ASIC solutions placed adjacent to the processor.

While solving the immediate crisis of signal integrity and density, on-ASIC integration pivots the engineering focus to the formidable new challenges of thermal management and system serviceability. For design engineers, unlocking the full performance of this new architecture now depends entirely on solving these complex, second-order challenges.

In a traditional front-panel pluggable architecture, the signal integrity challenge is a system-level problem. Signals must travel a long, lossy path from the chip through multiple microelectronic interconnects and substrates to the front-panel I/O.

The primary advantage of on-ASIC integration is shortening the electrical channel, thus reducing the core problem of signal degradation. For optics, this also breaks the costly cycle of having to re-engineer and validate the full electrical channel with each new speed generation, as engineers only need to solve for the short trace on the substrate. At  224Gbps-PAM-4 data rates, this reduction is critical, as it minimizes the need for the costly, power-intensive retimers required by conventional architectures.

By moving the optical engine onto the chip, power efficiency also improves significantly. This gain comes from reducing or eliminating the high-power Digital Signal Processors (DSPs) required in traditional pluggable modules to compensate for interconnect losses. Departing from traditional Multi-Source Agreement (MSA) standard form factors allows optical systems to increase faceplate density substantially. Replacing bulky pluggable transceiver cages with much denser, compact fiber optic connectors maximizes the use of valuable front-panel real estate.

Quantifying these gains is complex and application-specific. For the most advanced chips operating at the highest speeds, on-ASIC integration may be required, though other solutions work for many applications.

On-ASIC integration solves the first-order problem of signal loss. But, by doing so, it introduces a new and more formidable set of second-order challenges that shift the engineering focus.

Complexities of Thermal Management
Thermal management presents an immediate challenge with different complexities for copper and optics. While co-packaged copper (CPC) creates a competition for physical real estate due to cable density, co-packaged optics (CPO) must solve for the thermal incompatibility between its laser and the hot processor. For co-packaged optics (CPO), the primary heat source, the laser, cannot operate reliably in the same thermal zone as a hot processor and requires a new architectural approach. This often means designing custom liquid-cooled heat sinks to fit within the precise height and space constraints available around the die.

The Serviceability Risk
Serviceability creates a critical, high-stakes risk. With components now integrated onto the same expensive substrate as the high-value ASIC, a failure in a single, low-cost connector could jeopardize the entire processor package. Because the ASIC cannot be easily removed or replaced, the entire assembly becomes a single point of failure. This threat makes reworkability a primary design consideration and positions compression-based interconnects as a risk-reduced attachment option.

For CPO, the risk is even more acute. With current designs, the optical fibers are often permanently fixed to the optical engine on the substrate. A single broken fiber during assembly or service could render the entire package useless.

Beyond Standard Validation Procedures
Validation presents a final challenge because the unique on-substrate environment is not fully covered by standard EIA or Telecordia specifications. At 224G data rates, previously minor variables like slight variations in the substrate's physical warp can now significantly impact performance, creating a new class of potential failure modes that are difficult to predict.  These factors will become even more impactful at speeds beyond 224G.

Successfully navigating the second-order challenges of on-ASIC design demands a system-level engineering philosophy that addresses the complex interaction of electrical, mechanical and thermal properties.

New Approach to Serviceability and Rework
For the critical serviceability challenge, one promising approach for copper includes a compression-based interconnect. This design protects the high-value substrate and allows for simple, field-replaceable rework, thereby reducing risk to the processor.

For optics, this principle is extended to the development of separable fiber-to-chip interfaces, which are essential for creating a fully modular and serviceable CPO architecture.

Managing Thermal Challenges with an External Laser Source
In CPO, the architectural solution to the unique thermal problem is to decouple the primary heat source from the processor using an External Laser Source (ELS). This approach physically separates the high-power laser into a simple, pluggable and serviceable module, significantly reducing thermal stress while improving the laser's stability and long-term reliability.

Validating Performance in a New Environment
The solution to the validation challenge is a new and more rigorous testing philosophy.  Defining new test procedures that can successfully isolate and analyze the impact of subtle variables, such as substrate warp, on high-speed system performance is now a crucial requirement. This new level of rigor is essential for ensuring system reliability and preventing costly failures in a production environment.

The next frontier of on-ASIC integration will likely involve 3D chip stacking. Because components like memory and switch ASICs are often manufactured in different foundry nodes, stacking them vertically is the next logical step to create the shortest possible electrical connections. A parallel evolution is underway in the substrate materials themselves, with the industry actively exploring alternatives like glass and silicon to support these increasingly dense architectures.

The path forward, however, will be multifaceted. The long-predicted “death of copper” has yet to materialize, and on-ASIC integration is not an absolute requirement for every 224G application. Alternative architectures using interposers or daughter cards will remain viable, cost-effective options alongside optics for the foreseeable future.

Ultimately, mastering on-ASIC integration represents conquering the second-biggest challenge in creating the world's fastest systems, a vital discipline for any company looking to compete at the highest level of performance.

Molex translates on-ASIC architectural concepts into a portfolio of market-ready solutions that directly address the second-order challenges of integration.

Molex translates on-ASIC architectural concepts into a portfolio of market-ready solutions.  For CPC, the Impress Co-Packaged Copper Solution addresses the critical serviceability challenge through a compression-based approach. Utilizing 30 AWG twinax to support data rates of 224Gbps PAM-4 and beyond, the system provides a solderless interface that protects the high-value substrate. Such engineering allows for simple, field-replaceable rework without risking the processor.

For CPO, the first-to-market External Laser Source Interconnect System (ELSIS) addresses the core thermal and reliability challenges by moving the laser source into a separate, serviceable module. Molex also applies this system-level expertise to the next frontier of challenges, actively developing solutions for the difficult task of creating reliable, separable fiber-to-chip interfaces.

On-ASIC integration is a foundational component of the next-generation data center. Explore the comprehensive portfolio of Molex 224Gbps-PAM-4 high-speed data center technology.