"Inside-the-Box" Twinax Solutions - Design Considerations

The shift towards 56 and 112 Gbps PAM-4 signaling as the new normal continues to accelerate. Under intense pressure to increase data speed in tighter spaces without sacrificing signal integrity, data center and telecom infrastructure industries face a growing need for cost-effective solutions that maximize efficiency, reliability, power consumption, thermal performance and speed. 

At the same frequency, PAM-4 modulation offers twice the data rate speed compared to non-return to zero (NRZ) environments, but PAM-4 is more challenging to implement. PCB materials such as Megtron 6 and 8 reduce insertion loss and channel noise but are costly and may still not provide adequate channel margin without the use of retimers.

As a result, interest in low-loss, high-speed twinax solutions to bypass lossy printed circuit board materials is growing. These “inside the box” solutions provide greater channel margin, dramatically reducing insertion loss between a switch, router or server’s ASICs and front panel I/O.

Due to twinax’s superior signal integrity performance and ability to eliminate retimers in the channel, ASICs can do more with less power. Twinax solutions increase design flexibility by providing the opportunity to place ASICs anywhere, reduce the number of board layers and use smaller PCBs. In addition, thanks to the solution’s excellent signal integrity and low insertion loss capability, designers can use less costly passive copper solutions within the switch/router and throughout the rack without compromising performance.

Using twinax-enabled bypass solutions can also shorten time to market by eliminating the need for engineers to spend months optimizing each channel. However, designing with twinax solutions rather than standard PCB traces is significantly different than using current methodologies.

Many Top of Rack (TOR) designers are already seeking ways to best support Broadcom’s Tomahawk 4 ASIC. Initially supporting 1,024 56G PAM-4 differential pairs means designers need to figure out how to squeeze 64 ports of QSFP-DD into a TOR switch, including the need to move from a 1RU chassis to a 2RU system. Determining an optimal configuration/design means consideration of cost, channel lengths/margin and thermal requirements.

To optimize performance, cost and a path to market, designers must weigh the advantages and drawbacks of multiple configurations. Considerations include:

Consider a traditional method of using a 2×1 stacked DDQ press-fit or SMT connector.  Supporting 64, 400 Gbps ports might require a belly-to-belly configuration, use of retimers and significant trace routing engineering including the need for additional board layers. Alternatively, use of a bypass solution in a 1×2 vertical orientation offers superior SI performance compared to expensive PCB materials, elimination of retimers and improved cooling of 20/25 watt modules. Look for more on thermal cooling in a future post.

The flexibility of the Molex BiPass solution gives designers the freedom and the ability to mix and match components from a robust tool box to create products that successfully and cost-efficiently deliver next-generation data speed, enhanced thermal performance and superior signal integrity/channel margin.