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Computing architecture is only as good as the signal pathways used to transfer data. The fastest signaling architecture today requires a close look at three connectivity architecture options moving from a theoretical idea into practical alternatives. Evaluating the viability of 224G requires a close look at these three distinct interconnect architectures. Each option has its own advantages and trade-offs.
Navigating this decision matrix depends on a clear understanding of what drives the choice of one architecture over another. Each proposes a potential connectivity path to the speeds and feeds of both today and the next generation’s architectures.
Specifically, the focus is on co-packaged copper (CPC), near-package copper (NPC) and interposer card adapter (ICA)
Designing a 224G PAM-4 Architecture
When evaluating high-speed interconnects, system architecture serves as the primary driver for both channel electrical performance and overall thermal management. Selecting the right physical layer requires balancing signal integrity and fan-out with manufacturability, serviceability and ecosystem flexibility.
Evolution of Interconnect Architectural Paths for 224G to 448G
As the industry transitions from 112Gbps PAM-4 to 224Gbps PAM-4, engineers have established three viable architectures: CPC, NPC and ICA.
Although important to 224Gbps PAM-4 today, this same work is important to contemplating architectures addressing 448Gbps PAM-4 decisions. The industry must consider which of these architectures will continue and/or provide even greater value in a world of 448Gbps PAM-4 signaling.
Connectivity Architecture Options: Co-Packaged Copper vs. Near-Packaged Copper vs. Interposer Card Adapter
Meeting the demands of next-generation data rates requires a close evaluation of three primary physical layer configurations.
Co-Packaged Copper (CPC)
In this configuration, the connector is mounted directly on the substrate, creating the shortest electrical path with the fewest transitions for a 224Gbps PAM-4 channel architecture.
There are two methods to attach the connector to a substrate. Compression designs place the connector on the substrate and hold it in position using external clamping mechanisms.
Solder attachment electrically joins a connector header to the fixture using J-leads or a ball grid array (BGA). While this represents a traditional approach, fusing components directly to an expensive substrate introduces significant manufacturing risks and early yield complications.
Compression connectors bypass these soldering pitfalls entirely. By eliminating the need to solder directly to the silicon package, compression technology delivers a streamlined and low-risk path for integration into contract manufacturing and the broader supply chain.
When specifying a CPC solution, engineers evaluate one-piece and two-piece connector styles. One-piece connectors introduce mechanical risks as moving beams interact directly with the delicate substrate interface. A two-piece connector builds signal transfer quality directly into a dedicated mating interface. The sliding, re-mateable interface utilizes electroplated gold plating to deliver long-term contact reliability while protecting the substrate from mechanical damage during assembly.
Near Package Copper (NPC)
When weighing co-packaged copper versus near-packaged copper, NPC serves as a well-established architecture for 224Gbps PAM-4 data rates and the foundational predecessor to modern CPC designs. Placing the connector directly on the same PCB as the ASIC offers significant familiarity in manufacturing and supply chain operations.
NPC was developed to reduce PCB path loss by replacing portions of the PCB signal path with low-loss twinax cable. Compared with PCB-only solutions, internal Molex testing has demonstrated that NPC achieves a three-times reduction in series path loss.
Over the years, design practices for low-loss PCB laminates and highly optimized routing rules have become common knowledge, making NPC a tried-and-true industry baseline. Routing high-speed signals on the base board requires high-speed laminates across the board, making NPC best suited for architectures with additional high-speed ASIC-to-ASIC or in-chassis routing.
Interposer Card Adapter (ICA)
In some ways, the ICA is an extension of the CPC. The ICA defines an ASIC substrate interface and a method to create a system fan-out. The ICA itself is constructed using an HDI board manufacturing process, which enables the finer trace geometries and tighter tolerances required for high-speed signaling.
The ICA fanout feature addresses physical space constraints of the ASIC substrate escape routing by creating an option to fan out signals from the ASIC to the width of the connector cable array. Thus, the connector density is only limited by the size of the cable relative to the size of the ICA.
A side effect of using an interposer is a common electrical interface array to the top of a substrate. Similar to CPC, ICA implementations take advantage of top-layer routing in the ASIC substrate, thus avoiding high-speed signals traversing ground and signaling layers with long vias on the way to the BGA, optimizing 224G ASIC substrate escape routing.
However, some consideration is required relative to component cost. The price of the ICA includes an additional separable interface that impacts electrical performance.
The Molex Impress Advantage Across Architectures
To enable on-substrate architectures from 224G to 448G, Molex designed Impress Co-Packaged Copper Solutions. Impress supports any co-packaged copper architecture, and has the density and ruggedness required to meet the implementation of the highest-density system architectures.
For on-substrate designs, the compression-based termination of Impress lowers supply chain risk by allowing simple cable attachment. At the same time, its rugged mechanical design directs the physical force of heavy cable routing away from the delicate substrate and into the external chassis.
When applied to an ICA architecture, Impress adds ruggedness to the fan-out while providing necessary margin relative to insertion loss penalties. A slight modification to a soldered connection simplifies installation at the contract manufacturer by reducing hardware complexity and separating cable routing concerns from the substrate interface.
For NPC configurations, architects can leverage a broader portfolio of high-speed interconnects, including Impress, CX2DS or Inception solutions. Regardless of the chosen architecture, Molex co-engineers solutions that account for the ruggedness of the manufacturing process while delivering optimal signal integrity.
The ICA fanout feature addresses physical space constraints of the ASIC substrate escape routing by creating an option to fan out signals from the ASIC to the width of the connector cable array. Thus, the connector density is only limited by the size of the cable relative to the size of the ICA.
A side effect of using an interposer is a common electrical interface array to the top of a substrate. Similar to CPC, ICA implementations take advantage of top-layer routing in the ASIC substrate, thus avoiding high-speed signals traversing ground and signaling layers with long vias on the way to the BGA, optimizing 224G ASIC substrate escape routing.
However, some consideration is required relative to component cost. The price of the ICA includes an additional separable interface that impacts electrical performance.
Optimizing the Full Channel Architecture
Ultimately, optimizing a data center network rarely relies on a single interconnect strategy. There is considerable value in considering a mix of alternatives and making use of the advantages of each option.
For instance, a CPC or ICA could be considered for high-speed, long-reach connectivity that exits the chassis. Alternatively, a 1024 DP or even 2048 DP, combined with another 512 to 1024 DP of NPC connectivity for high-speed links inside the box, may be the best mix. This approach creates an architecture optimized for the highest speeds and most feeds between the ASICs.
As system architects weigh these choices, Molex can help clarify design options and coordinate mechanical solutions to fit substrates for any switching or compute ASIC. Discover how to optimize your next-generation interconnect strategy by exploring Co-Packaged Copper for AI Data Centers.
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